The present invention relates generally to integrated circuits, and more specifically, to a method of automation of logic synthesis and implementation for reducing logic and delay through latch polarity inversion.
In synchronous logic designs, latches or flip-flops are the sequential blocks that synchronize the logic flow. Due to the complexity of logic designs, the logic flows are written in hardware description languages (HDL) such as very-high-speed integrated circuit “VHSIC” (VHDL), and then synthesized into digital logic circuits. The synthesis process includes inserting logic between the latches to implement logic functions using inverters and/or other logic gates. A combinational synthesis process is repeated for all logic functions within the design. The signal polarity of each logic function is correctly implemented within the latch boundaries however maintaining signal polarity across latch boundaries may lead to inefficient use of inverters and/or logic gates, thereby causing extra path delay and circuit power.